1. Field of the Invention
The present invention relates to a planarization process on a common source line of a flash memory device and, more particularly, to an etching back process on a polysilicon layer to improve the topographic planarization of the common source line.
2. Description of the Related Art
A flash memory cell comprises a floating gate for storing charges and a control gate for controlling the voltage of a world line, in which the voltages of the world line and source/drain electrodes are coordinated to control the charge-stored capacity of the floating gate and decide the on/off state of a transistor. Thus, the flash memory is also called an erasable programmable read only memory, or EPROM. For early flash memory devices, a gate structure is formed by stacking the control gate on the floating gate. As for the recent flash memory device, a gate structure is formed by laterally arranging the control gate and the floating gate, in which an insulating spacer is formed on the sidewall of the floating gates, after which a common source line is formed in a space between two adjacent floating gates, and then the control gate is formed outside the floating gates.
Generally, the material of the common source line is polysilicon. However, due to limitations in the polysilicon deposition, the topographic planarization of the polysilicon layer is difficult to control in subsequent etching back process, causing a connection between the adjacent insulating spacers to fail the isolation result.
FIGS. 1A to 1C are sectional diagrams showing a common source line process according to the prior art. As shown in FIG. 1A, a silicon substrate 10 is provided with a pad oxide layer 12, a floating gate layer 14, a dielectric layer 16, and an insulating spacer structure 18. Preferably, the floating gate layer 14 is polysilicon, the dielectric layer 16 is silicon nitride, and the insulating spacer structure 18 is TEOS-oxide. In addition, a contact hole 20 is formed between two adjacent floating gate layers 14 to expose a source/drain region of the silicon substrate 10. Next, as shown in FIG. 1B, a polysilicon layer 22 of 6000 xc3x85 thickness is deposited on the entire surface of the silicon substrate 10. Since the surface profile of the polysilicon layer 22 varies depending on the topography of the silicon substrate 10, a sunken portion is found in the polysilicon layer 22 over the contact hole 20, and the depth D1 of the sunken portion is approximately 1000 xc3x85. Thereafter, as shown in FIG. 1C, using an etching back process, such as a reactive ion dry etching process, the polysilicon layer 22 outside the contact hole 20 is removed, and the polysilicon layer 22 remaining in the contact hole 20 serves as a common source line 24.
However, during the etching back process, it is difficult to adjust the process conditions of the dry etching to accurately control the topographic planarization of the polysilicon layer 22. Also, this may cause overetching on the polysilicon layer 22 over the contact hole to form a corresponding sunken portion on the top of the common source line 24, in which the thickness D2 of the sunken portion is 130xcx9c140 xc3x85. Furthermore, as the overetching time is increasing, the thickness of the dielectric layer 16 is decreasing, resulting in a decreased CD value of the line width by measuring the common source line 24, and a failed isolation provided by the insulating spacer structure 18.
Seeking to solve this problem, a chemical mechanical polishing (CMP) method is employed to level off the polysilicon layer 22 to improve the topographic planarization of the common source line 24. The CMP method, however, has disadvantages of expensive process costs, pollutant byproducts, and process defects, so integrating the CMP method into the common source line process cannot be applied to mass production.
The present invention uses an etching back process to improve topographic planarization of a polysilicon layer to solve the problems caused by the prior method.
In the etching back process, a polysilicon layer is formed to fill a contact hole between two adjacent insulating structures and cover the entire surface of a semiconductor substrate to a predetermined height, in which a sunken portion is formed in the polysilicon layer over the contact hole. Then, a bottom antireflective coating (BARC) layer is formed to fill the sunken portion and cover the entire surface of the polysilicon layer. Next, in a first etching step, the BARC layer outside the sunken portion of the polysilicon layer is removed and the BARC layer in the sunken portion of the polysilicon layer is retained to flatten the bottom of the sunken portion. Thereafter, in a second etching step, the etching rate of the polysilicon is decreased while that of the BARC layer is increased to remove a part of the polysilicon layer outside the sunken portion and retain some of the BARC layer inside the sunken portion, in which the BARC layer remaining in the sunken portion protrudes from the polysilicon layer. Next, the polysilicon layer outside the contact hole is completely removed.
Accordingly, it is a principal object of the invention to improve the topographic planarization of the common source line to obtain a superior flat top.
It is another object of the invention to separate the adjacent insulating spacer structures from each other to ensure the required isolating result.